Most semiconductor vendors (like Qualcomm, Nordic, or MediaTek) provide simplified versions of the SPMI register maps in their proprietary datasheets for engineers implementing their chips.
The MIPI SPMI specification defines a high-speed, low-power interface for power management in SoC designs. The interface is designed to be scalable, flexible, and efficient, allowing for the management of multiple power domains and voltage regulators. mipi spmi specification pdf
To change a PMIC’s output from 1.1V to 1.2V: To change a PMIC’s output from 1
Supports 8-bit or 16-bit addressing, allowing for flexible register access. allowing for improved power efficiency
The bus itself can enter a "Shutdown" or "Low Power" state when no data is being transmitted, ensuring the communication interface doesn't become a drain on the battery it is meant to preserve. Technical Specifications Table Specification Detail Two-wire, multi-master/multi-slave Bus Speed Up to 26 MHz Addressing 4-bit Slave Identifier (SID) Voltage Levels Typically 1.2V or 1.8V (low-voltage CMOS) Arbitration Non-destructive, priority-based Benefits of Using SPMI over I2C or SPI
The MIPI SPMI specification is a widely adopted standard for power management in mobile systems. Its high-speed, low-power interface enables efficient communication between processors or SoCs and power management devices, allowing for improved power efficiency, flexibility, and user experience. The specification is designed to be scalable, flexible, and extensible, making it suitable for a wide range of mobile devices.